1. Field
This invention relates generally to DC-DC power converters and more particularly to an improved series inductor/parallel inverter power stage and power staging method for a transistor controlled DC-DC power converter.
2. Prior Art
One common prior art DC-DC power converter receives current from a DC source, which may be an unregulated source, chops it with a switching device or chopper such as a transistor, integrates the chopped signal with an inductive/capacitive network, converts the integrated DC signal to AC with a transistor inverter, transforms the AC to another voltage in a transformer, and rectifies the transformer output to provide the desired converter DC output voltage.
In this existing converter power stage, the integrating capacitance is located in the input to the transformer, between the chopper and the inverter. The chopper transistor is turned on and off with a duty cycle proportional to the deviation of the converter output voltage from a preset voltage level to be maintained. The inverter power transistors are turned on and off alternately with equal on and off times such that one or the other of these transistors is always conducting.
This type of converter power stage is subject to large current and voltage transients whih can easily damage the converter transistors or cause them to fail, unless they are highly over-rated. These transients may be due to overlapping of the inverter transistor on times, transformer core saturation resulting from unequal on times of the inverter transistors, and output shorts.
Another disadvantage of this converter power stage resides in the fact that two transistors, namely the chopper transistor and one or the other of the inverter transistors, are always situated in series in the main power flow path. This results in excessive power dissipation.
It has been proposed in the past to avoid excessive transients in such converter power stages by placing the input integrating capacitance in the transformer output and connecting as inductor choke in series with the power transformer primary winding. An example of this form of converter power stage, which is commonly referred to as a series inductor power stage, is described in my prior U.S. Pat. No. 4,034,280. The series inductor provides an impedance in series with the power transistors for limiting peak current flow during output shorts, power transformer saturation, and power transistor overlap. The power stage of the latter patent, however, like that described first, is subject to excessive power dissipation due to the presence of two transistors in series in the main power flow path at all times.
Utilization of such a converter power stage for high power applications also presents a problem. Thus, the maximum power rating of existing transistors places a severe constraint on the maximum power levels which may be handled.